In recent years, thanks to the introduction of the NoC paradigm, on-chip interconnect technology has been able to sustain the development of an ever-increasing number of SoC products. However, to render possible development of a new generation of SoCs it is necessary to perform a further step ahead. In effect, the complexity of SoCs renders extremely complex the problem of designing on-chip interconnect with a given quality of service (QoS) so as to force designers to make considerable efforts in terms of time and activity.
In the past, various techniques of implementation of QoS have adopted an approach that can be defined as “static”. The main disadvantage of this approach lies in the fact that the result depends markedly upon the particular interconnect architecture. For example, the bandwidth engaged by a given IP functioning as initiator in communicating with a given IP functioning as target depends upon the particular routing path followed during the communication and upon the traffic that flows through the same path or part thereof. It may consequently be stated that the solutions based upon a static approach do not enable an end-to-end QoS proper to be obtained.
Another approach suggested in the literature for implementing a good QoS consists in adopting so-called virtual channels (VCs). This approach enables better results to be obtained as compared to a pure static solution, even though at least three orders of problems arise.
A first order of problems is that of partial QoS: virtual channels enable separation of the classes of service, but do not provide any mechanism for managing the performance within one and the same class of service. In other words, within one and the same class the same problems typical of the static approach are re-proposed.
A second order of problems is linked to costs. To implement separate classes of service it is necessary to use them in the entire communication infrastructure, which introduces additional costs that are hard to accept since the entire logic must be duplicated.
A third order of problems is linked to the fact that frequently the components that function as initiators (CPUs, video/audio decoders, DMAs, etc.), in order to ensure consistency, wait for the interconnect to be able to supply the data to the destination so as to guarantee the order. When this need arises it is not possible to use the virtual channels.